FIG. 1 is a block diagram of a prior art Delay-Locked Loop (DLL) 100. In the DLL 100, an externally supplied clock (CLK) is buffered by clock buffer 101 to provide a reference clock (CLK_REF). As understood by those skilled in the art, the CLK signal could be, for example, a data strobe signal (DQS or DQSb signal) transmitted from a memory controller to a memory device. However, it is of course possible that the CLK signal will, in alternative examples, be some other type of clock signal. Continuing on with the discussion of the DLL block diagram of FIG. 1, it will be seen that CLK_REF is coupled to a Voltage Controlled Delay Line (VCDL) 102 and a phase detector 104. The VCDL 102 produces an output clock (CLK_OUT), which is a delayed version of CLK_REF and is routed to various circuits within the device containing the DLL 100. As shown, CLK_OUT is also routed to the phase detector 104, and thus the phase detector 104 receives CLK_OUT as a feedback clock signal, referred to as CLK_FB.
With respect to phase shifting by the DLL, those skilled in the art will appreciate that in some memory systems where the timing signal being phase shifted is DQS or DQSb, the timing signal will be shifted by 90 degrees so that the edges of the timing signal are centered with respect to its associated data. Also, as clock frequencies in memory systems become increasingly higher, the ability to make fine-tuned phase shifting adjustments will continue to become increasingly useful.
Still with reference to the illustrated DLL 100, the phase detector 104 generates phase control signals (UP/DOWN) dependent on the phase difference between CLK_REF and CLK_FB. The phase control signals (UP/DOWN) of the phase detector 104 are provided to a charge pump 105, the output thereof which is conditioned by a loop filter 106 to provide a variable bias voltage VCTRL 110. Those skilled in the art will understand that loop filter 106 can include any number of passive components arranged in a desired configuration. The bias voltage VCTRL selects the delay to be added to CLK_REF by the VCDL 102 to provide for the proper phase relation between CLK_FB and CLK_REF. VCDL 102 can be implemented with a variety of known circuits.
Another type of feedback system known to those skilled in the art of memory design is a Phase-Locked Loop (PLL). FIG. 2 is a block diagram of a prior art PLL 200. An externally supplied clock (CLK) is buffered by clock buffer 201 to provide a reference clock (CLK_REF) that is coupled to a phase detector 204. The phase detector 204 generates phase control signals (UP/DOWN) dependent on the phase difference between CLK_REF and CLK_FB.
The phase control signals (UP/DOWN) of the phase detector 204 are provided to a charge pump 205, the output thereof which is conditioned by a loop filter 206 to provide a variable bias voltage VCTRL 210. The bias voltage VCTRL controls a Voltage Controlled Oscillator (VCO) 202 which outputs a clock signal CLK_OUT. The frequency of the output clock signal CLK_OUT is proportional to the bias voltage VCTRL 210. Also, the CLK_OUT signal is optionally coupled to a divider 203 to produce the CLK_FB signal.
Having now described the general architecture of PLLs and DLLs, it will be understood that the operation of a particular DLL will not always be independent of other PLLs present in the larger memory design. For example, two 90 degree phase shifted DQS and DQSb signals available within a master PLL can be provided to a slave DLL. It will be understood that, in such circumstances, the slave DLL output is dependent upon the phase and frequency information that the master PLL provides. This dependency is not necessarily disadvantageous, and it has been found, generally speaking, that slave DLLs relying upon master PLLs, as described above, provide output clocks that are, for a large majority of presently existing applications, properly phase shifted relative to the reference clock.
While it is preferable that the output clock signal of a DLL be properly phase shifted relative to the reference clock signal, future improvements in DLLs may relate to other aspects of the DLL, such as reduced power consumption, for example. In this regard, phase detector circuits in accordance with at least some example embodiments permit implementation of DLLs with reduced power consumption.